1. Field of the Invention
This invention relates to a sense amplifier circuit, and more particularly to a current detecting type sense amplifier circuit for amplifying data read out from a memory cell.
2. Description of the Related Art
Conventionally, a current detecting type sense amplifier is used as a sense amplifier circuit for bipolar memories or Bi.multidot.CMOS (bipolar.multidot.complementary MOS) memories. This type of sense amplifier circuit is disclosed in Japanese Patent Publication No. 60-34294, for example. In such a sense amplifier circuit as is disclosed in the above Patent Publication, since the amplitude of a voltage occurring between paired data lines at the time of readout of stored data from a memory cell is relatively small, a readout current can be transmitted to a load section without substantially driving a parasitic capacitor of the data line pair. Therefore, it becomes possible to suppress the delay in data transfer caused by the charging and discharging operations of the parasitic capacitor of the data line pair.
However, with an increase in the memory capacity in recent years, the data line is formed thinner and longer so that the parasitic resistance of the data line may tend to become larger. As the parasitic resistance of the data line increases, the amplitude of a voltage occurring between paired data lines at the time of readout of stored data becomes larger, causing a relatively large delay in the data line section.
In order to solve the above problem, various types of sense amplifiers have been proposed to improve the delay characteristic in the data line section. One of them is proposed by the inventor of this invention and disclosed in Japanese Patent Disclosure No. 3-52194. In a sense amplifier circuit disclosed in the above Patent Disclosure, the data line pair is formed in a hierarchical structure (the data line pair is divided into first- and second level data line pairs and a readout current transmission circuit is formed between the first- and second-level data line pairs) to reduce the length of the data line on each level. With the above structure, since the length of the first-level data line pair can be reduced and the parasitic resistance and parasitic capacitance can be reduced, the delay in the data line can be significantly reduced. Further, since the wiring length of the second-level data line can be reduced by adequately arranging the second-level data line, the wiring resistance thereof can be reduced. In addition, since the collector capacitor of a bipolar transistor used in the readout current transmission circuit is simply provided for each transmission circuit, the data line capacitor can be made relatively small. As a result, since the delay in the second-level data line section can be reduced, the total delay in the entire data line can be significantly improved. Further, it is only required to activate only one of a plurality of emitter-coupled differential pairs connected to a plurality of first-level data line pairs even though the data line pairs are formed in the hierarchical structure, the current consumption in the differential amplifier may be made substantially the same as that in the prior art.
However, in the circuit system disclosed in the above Patent Disclosure, since two reference potentials are required and bipolar circuits of three stages are series-connected, the power source voltage margin may be deteriorated by an amount corresponding to the base-emitter voltage (forward voltage Vf of a diode) of a bipolar transistor used in the readout current transmission circuit in comparison with the conventional circuit system. Particularly, in a Bi.multidot.CMOS memory or the like using a circuit of miniaturized CMOS structure, the power source voltage tends to be lowered, but in this case, the sense amplifier circuit of a type disclosed in the above Patent Disclosure cannot be used.
A sense amplifier disclosed in IEEE JOURNAL OF SOLID-STATE CIRCUITS. VOL. 25, NO. 5, OCTOBER 1990 pp 1057 to 1062 is known as another means for solving the above problem. The sense amplifier circuit disclosed in the above article has a feature that a resistor is connected between the paired data lines of the conventional current detecting type sense amplifier circuit and a by-pass current is supplied to the resistor to equalize the paired data lines. With this feature, a difference between currents flowing in the paired data lines is reduced and the delay in the data line section becomes small. That is, the amplitude of a voltage between the paired data lines can be reduced by increasing the conductance of the resistor connected between the paired data lines, thereby increasing the by-pass current flowing in the resistor. However, at this time, a problem that the output amplitude of the sense amplifier becomes small occurs. In order to solve this problem, the resistance of a load resistor of a common load circuit may be increased. In this case, however, if the conductance of the resistor connected between the paired data lines is increased and the resistance of the load resistor of the common load circuit is increased, then a new problem that the bipolar transistor of the common load circuit is saturated occurs. This is because the total sum of the readout currents transmitted to the common load circuit is equal to the total current (the sum of the complementary currents) always flowing in the sense amplifier circuit. Therefore, it is impossible to excessively increase the conductance of the resistor connected between the paired data lines and the delay time in the data line section may not be significantly reduced.